This invention relates generally to arrays of non-volatile memory cells which each includes a field effect transistor with a floating gate, and, more specifically, to EEPROM and flash EEPROM arrays and processes of forming them.
Field effect transistors having floating (unconnected) gates have long been utilized to form a non-volatile, semiconductor memory. Electrons are moved onto or removed from the floating gate of a given transistor memory cell in order to program or erase its state. The state of such a transistor memory cell is determined by applying a voltage across its source and drain and then measuring the current which passes through the transistor. The programmed level of charge on the floating gate is retained for a long period of time, essentially indefinitely. Memory arrays of such transistor cells are commonly available in various forms, such as PROMs, EPROMS, EEPROMs and flash EEPROMs. Currently, flash EEPROM technology is being used for large capacity semiconductor non-volatile memory, either in place of, or in combination with, a magnetic disk drive memory system.
Typically, such a semiconductor memory system is made up of a number of integrated circuit chips that each contain a two dimensional array of EEPROM cells, plus other integrated circuit chips providing a controller and other system operating support. One type of memory array integrated circuit chip includes elongated, spaced apart source and drain regions formed in a surface of a semiconductor substrate. These source and drain regions form the bit lines of the memory. A two dimensional array of floating gates has each floating gate positioned in a channel region between adjacent source and drain regions. An elongated control gate is positioned over each row of floating gates in a direction transverse to the source and drain regions. The control gates are the word lines of the memory array.
One type of cell used in such a memory array extends each of its floating gates over only part of its channel between the source and drain regions, while the control gate is positioned over the remaining portion of the channel. This is termed a "split-channel" type of EEPROM cell and effectively connects a select transistor in series with the floating gate transistor in order to isolate the floating gate transistor from the bit lines when its control gate (word line) is not active. An alternative type of EEPROM cell extends its control gate completely across the channel region, thus eliminating the select transistor and allowing the memory cell to be made smaller. However, the absence of the select transistor in each cell places additional constraints on operating a memory array of such cells.
One class of EEPROM devices employs an erase gate positioned adjacent the floating gate of each cell, with a thin dielectric therebetween, in order to transfer electrons from the floating gate to the erase gate when all the relative voltages are appropriately set. Flash EEPROM systems use a common erase gate for a sector or other block of cells, thus enabling their simultaneous erasure in a "flash." An alternative class of EEPROM devices does not use the separate erase gate, but rather removes the electrons from the floating gate through the substrate when all the appropriate voltages are set. In such flash EEPROM systems, the sectors or other blocks of cells are isolated from one another on the substrate in order that the individual blocks may be selectively and individually erased.
Since a high density memory cell array is always desired, self-aligned techniques are used during manufacture of the circuit whenever possible. One way of forming an array with erase gates is to deposit the erase gates in between adjacent rows of memory cells that have already been largely formed, and to couple each erase gate with the floating gates of the adjacent rows on both sides. Such a structure is usually operated by erasing each pair of adjacent rows of cells together. This works well so long as an even number of two or more rows of memory cells are included in the individual sectors or other blocks of cells that are erased together. But recent semiconductor processes have resulted in the density of memory cells increasing to the point where a number of cells required for common sector sizes can be provided in one row cells, or even by one-half a row or less.
There is, however, an innovative way of operating such a memory array to erase only one of the adjacent rows at a time. As described in a copending patent application of Samachisa et al., Ser. No. 08/453,124, filed May 31, 1995, application of different voltages to the control gates of the rows on opposite sides of an erase gate allows a selected one of the two rows to be erased at a time. But it still can be desirable to provide each row with its own erase gate.
Therefore, it is a primary object of the present invention to provide memory cell array structures that have a separate erase gate for each of the rows of memory cells without having to sacrifice a high cell density.
It is another primary object of the present invention to provide improved techniques for making such arrays.